UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 995

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
Cautions 1. To resume the normal operation mode with ABT from the message buffer 0, set the ABTCLR bit to
Remark
2. Whether the automatic block transmission engine is cleared by setting the ABTCLR bit to 1 can
3. Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in the initialization
4. Do not set the TRQ bit of the ABT message buffers to 1 by software in the normal operation mode
5. The C0GMABTD register is used to set the delay time that is inserted in the period from
6. If a transmission request is made for a message other than an ABT message and if no delay time
7. Do not clear the RDY bit to 0 when the ABTTRG bit = 1.
8. If a message is received from another node in the normal operation mode with ABT, the message
m = 00 to 31
1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to
1, the subsequent operation is not guaranteed.
be confirmed if the ABTCLR bit is automatically cleared to 0 immediately after the processing of
the clearing request is completed.
mode, the proper operation is not guaranteed after the mode is changed from the initialization
mode to the ABT mode.
with ABT. Otherwise, the operation is not guaranteed.
completion of the preceding ABT message to setting of the TRQ bit for the next ABT message
when the transmission requests are set in the order of message numbers for each message for
ABT that is successively transmitted in the ABT mode. The timing at which the messages are
actually transmitted onto the CAN bus varies depending on the status of transmission from other
stations and the status of the setting of the transmission request for messages other than the
ABT messages (message buffers 8 to 31).
is inserted in the interval in which transmission requests for ABT are automatically set
(C0GMABTD register = 00H), messages other than ABT messages may be transmitted regardless
of their priority in regards to the ABT message.
may be transmitted after the time of one frame has elapsed even when C0GMABTD register = 00H.
CHAPTER 20 CAN CONTROLLER
Page 995 of 1509