UPD70F3765GF-GAT-AX Renesas Electronics America, UPD70F3765GF-GAT-AX Datasheet - Page 353

• Manufacturer Part Number: UPD70F3765GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3765GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
with the count clock, and the counter starts counting. At this time, the output of the TOABn0 pin is inverted. Additionally,
the set value of the TABnCCR0 register is transferred to the CCR0 buffer register.
to 0000H, the output of the TOABn0 pin is inverted, and a compare match interrupt request signal (INTTABnCC0) is
generated.
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
TABnCTL1
When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
The interval can be calculated by the following expression.
Interval = (Set value of TABnCCR0 register + 1) × Count clock cycle
Note This bit can be set to 1 only when the interrupt request signals (INTTABnCC0 and INTTABnCCk) are
Remark
TABnCTL0
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
masked by the interrupt mask flags (TABnCCMK0 to TABnCCMKk) and the timer output (TOABnk) is
performed at the same time. However, the TABnCCR0 and TABnCCRk registers must be set to the
same value (see 8.5.1 (2) (d) Operation of TABnCCR1 to TABnCCR3 registers) (k = 1 to 3).
TABnSYE
n = 0, 1
0
TABnCE
0/1
TABnEST
Figure 8-4. Register Setting for Interval Timer Mode Operation (1/2)
0
0
TABnEEE
0/1
Note
0
0
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0
0
TABnMD2 TABnMD1 TABnMD0
0
TABnCKS2 TABnCKS1 TABnCKS0
0/1
0
0/1
0
0/1
0, 0, 0:
Interval timer mode
0: Operate on count
1: Count with external
clock selected by bits
TABnCKS0 to TABnCKS2
event count input signal
Select count clock
0: Stop counting
1: Enable counting
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