EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 110

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 2 Port Integration Module (S12XEPIMV1)

The following table summarizes the effect of the various conﬁguration bits, i.e. data direction (DDR),

output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS) on the pin function and pull

device activity.

The conﬁguration bit PS is used for two purposes:

1. Conﬁgure the sensitive interrupt edge (rising or falling), if interrupt is enabled.

2. Select either a pull-up or pull-down device if PE is active.

= Unimplemented or Reserved

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor