EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 115

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other modes the data source

Freescale Semiconductor

Address 0x0005 (PRR)

Address 0x0006 (PRR)

is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

is depending on the data direction value.

Write: Anytime. In emulation modes, write operations will also be directed to the external bus.

Port D general purpose input/output data—Data Register

Port D pins 7 through 0 are associated with data I/O lines DATA[7:0] respectively in expanded modes.

When not used with the alternative function, these pins can be used as general purpose I/O.

If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise

the buffered pin input state is read.

Port D Data Register (PORTD)

Port C Data Direction Register (DDRC)

Figure 2-7. Port C Data Direction Register (DDRC)

Table 2-9. PORTD Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 2-6. Port D Data Register (PORTD)

Chapter 2 Port Integration Module (S12XEPIMV1)

Access: User read/write