EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 250

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 5 External Bus Interface (S12XEBIV4)
This register controls input pin threshold level and determines the external address and data bus sizes in
normal expanded mode. If not in use with the external bus interface, the related pins can be used for
alternative functions.
External bus is available as programmed in normal expanded mode and always full-sized in emulation
modes and special test mode; function not available in single-chip modes.
1. EWAIT function is enabled if at least one CSx line is configured respectively in MMCCTL0. Refer to S12X_MMC section and
250
ITHRS
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Table
ASIZ[4:0]
ITHRS
0
1
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
HDBE
Field
4–0
7
5
5-6.
External Signal
TAGHI, TAGLO
TAGHI, TAGLO
DATA[15:8]
DATA[15:8]
DATA[7:0]
DATA[7:0]
Reduced Input Threshold — This bit selects reduced input threshold on external data bus pins and specific
control input signals which are in use with the external bus interface in order to adapt to external devices with a
3.3 V, 5 V tolerant I/O.
The reduced input threshold level takes effect depending on ITHRS, the operating mode and the related enable
signals of the EBI pin function as summarized in
0 Input threshold is at standard level on all pins
1 Reduced input threshold level enabled on pins in use with the external bus interface
High Data Byte Enable — This bit enables the higher half of the 16-bit data bus. If disabled, only the lower 8-
bit data bus can be used with the external bus interface. In this case the unused data pins and the data select
signals (UDS and LDS) are free to be used for alternative functions.
0 DATA[15:8], UDS, and LDS disabled
1 DATA[15:8], UDS, and LDS enabled
External Address Bus Size — These bits allow scalability of the external address bus. The programmed value
corresponds to the number of available low-aligned address lines (refer to
ADDR[22:0] start up as outputs after reset in expanded modes. This needs to be taken into consideration when
using alternative functions on relevant pins in applications which utilize a reduced external address bus.
EWAIT
EWAIT
ASIZ[4:0]
00000
00001
00010
Table 5-4. Input Threshold Levels on External Signals
Standard
Standard
NS
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 5-3. EBICTL0 Field Descriptions
Table 5-5. External Address Bus Size
Standard
Standard
SS
Available External Address Lines
Description
Table
if HDBE = 1
enabled
Standard
Reduced
Reduced
Reduced
ADDR1, UDS
if EWAIT
NX
None
5-4.
UDS
(1)
Reduced
Standard
Reduced
Standard
ES
Table
5-5). All address lines
Standard
Reduced
Reduced
Reduced
if EWAIT
enabled
EX
Freescale Semiconductor
1
Standard
Standard
Reduced
ST