EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 207

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and
0x3FFF out of reset.
The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).
3.3.2.8
Read: Anytime
Write: Anytime
These eight index bits are used to page 1 KByte blocks into the EEPROM page window located in the local
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see
accessing up to 256 KByte of EEPROM (in the Global map) within the 64 KByte Local map. The
EEPROM page index register is effectively used to construct paged EEPROM addresses in the Local map
format.
Freescale Semiconductor
Address: 0x0017
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
RP[7:0]
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7–0
W
R
EP7
RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
EEPROM Page Index Register (EPAGE)
1
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
EP6
1
6
Figure 3-15. EEPROM Page Index Register (EPAGE)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 3-14. RPAGE Field Descriptions
EP5
5
1
CAUTION
EP4
1
4
Description
EP3
1
3
Chapter 3 Memory Mapping Control (S12XMMCV4)
EP2
2
1
Figure
3-16). This supports
EP1
1
1
EP0
0
0
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