EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 1243

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Freescale Semiconductor

Load capacitance C

Thresholds for delay measurement points

Timing speciﬁed for equal load on all SPI output pins. Avoid asymmetric load.

1. If conﬁgured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, bit 2... MSB.

the timing diagram for master mode with transmission format CPHA = 0 is depicted.

on all outputs

MC9S12XE-Family Reference Manual Rev. 1.23

Figure A-7. SPI Master Timing (CPHA = 0)

Table A-27. Measurement Conditions

Bit MSB-1. . . 1

(20% / 80%) V

Full drive mode

Appendix A Electrical Characteristics