EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 361

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.3.1.1
All module level switches and flags are located in the XGATE Module Control Register
Module Base +0x00000
Read: Anytime
Write: Anytime
Freescale Semiconductor
Reset
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
XGDBGM
XGFRZM
XGSSM
XGEM
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
W
R
15
14
13
12
XGEM
15
0
0
XGE Mask — This bit controls the write access to the XGE bit. The XGE bit can only be set or cleared if a "1" is
written to the XGEM bit in the same register access.
Read:
Write:
0 Disable write access to the XGE in the same bus cycle
1 Enable write access to the XGE in the same bus cycle
XGFRZ Mask — This bit controls the write access to the XGFRZ bit. The XGFRZ bit can only be set or cleared
if a "1" is written to the XGFRZM bit in the same register access.
Read:
Write:
0 Disable write access to the XGFRZ in the same bus cycle
1 Enable write access to the XGFRZ in the same bus cycle
XGDBG Mask — This bit controls the write access to the XGDBG bit. The XGDBG bit can only be set or cleared
if a "1" is written to the XGDBGM bit in the same register access.
Read:
Write:
0 Disable write access to the XGDBG in the same bus cycle
1 Enable write access to the XGDBG in the same bus cycle
XGSS Mask — This bit controls the write access to the XGSS bit. The XGSS bit can only be set or cleared if a
"1" is written to the XGSSM bit in the same register access.
Read:
Write:
0 Disable write access to the XGSS in the same bus cycle
1 Enable write access to the XGSS in the same bus cycle
FRZM
XGATE Control Register (XGMCTL)
XG
14
0
0
This bit will always read "0".
This bit will always read "0".
This bit will always read "0".
This bit will always read "0".
= Unimplemented or Reserved
DBGM
XG
13
0
0
SSM
Table 10-2. XGMCTL Field Descriptions (Sheet 1 of 3)
XG
12
0
0
Figure 10-3. XGATE Control Register (XGMCTL)
FACTM
MC9S12XE-Family Reference Manual Rev. 1.23
XG
11
0
0
10
0
0
SWEFM
XG
0
0
9
XGIEM
0
0
8
Description
XGE
0
7
XGFRZ XGDBG XGSS XGFACT
6
0
0
5
0
4
Chapter 10 XGATE (S12XGATEV3)
0
3
Figure
0
0
2
SWEF
XG
1
0
10-3.
XGIE
0
0
361