EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 520

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 13 Analog-to-Digital Converter (ADC12B16CV1)
Write: Anytime (No effect on (CC3, CC2, CC1, CC0))
13.3.2.8
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
520
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
ETORF
CC[3:0]
FIFOR
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
SCF
3–0
7
5
4
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN=1), the flag is set after each one is completed. This flag is cleared
when one of the following occurs:
0 Conversion sequence not completed
1 Conversion sequence has completed
External Trigger Overrun Flag — While in edge trigger mode (ETRIGLE=0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
0 No External trigger over run error has occurred
1 External trigger over run error has occurred
Result Register Over Run Flag — This bit indicates that a result register has been written to before its
associated conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode
because the flag potentially indicates that result registers are out of sync with the input channels. However, it is
also practical for non-FIFO modes, and indicates that a result register has been over written before it has been
read (i.e. the old data has been lost). This flag is cleared when one of the following occurs:
0 No over run has occurred
1 Overrun condition exists (result register has been written while associated CCFx flag was still set)
Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC3=0, CC2=1,
CC1=1, CC0=0 indicates that the result of the current conversion will be in ATD Result Register 6. If in non-FIFO
mode (FIFO=0) the conversion counter is initialized to zero at the begin and end of the conversion sequence. If
in FIFO mode (FIFO=1) the register counter is not initialized. The conversion counters wraps around when its
maximum value is reached.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1.
ATD Compare Enable Register (ATDCMPE)
A) Write “1” to ETORF
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
A) Write “1” to FIFOR
B) Write to ATDCTL0,1,2,3,4, ATDCMPE or ATDCMPHT (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC=1 and read of a result register
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 13-17. ATDSTAT0 Field Descriptions
Description
Freescale Semiconductor