EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 421

BOARD EVAL FOR MC9S12XEP100

EVB9S12XEP100

Manufacturer Part Number
EVB9S12XEP100
Description
BOARD EVAL FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of EVB9S12XEP100

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
BRK
Operation
Put XGATE into Debug Mode (see
breakpoint to the S12X_DBG module (see section 4.9 of the S12X_DBG Section).
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
BRK
N
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Not affected.
Not affected.
Not affected.
Not affected.
Z
V
Source Form
It is not possible to single step over a BRK instruction. This instruction does
not advance the program counter.
C
MC9S12XE-Family Reference Manual Rev. 1.23
Address
Section 10.6.1.0.1, “Entering Debug
Mode
INH
0
Break
NOTE
0
0
0
0
0
Machine Code
0
0
0
Mode”) and signals a software
0
0
Chapter 10 XGATE (S12XGATEV3)
0
0
0
BRK
0
0
Cycles
PAff
421

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