EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 1240

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Appendix A Electrical Characteristics

Phase Locked Loop

Jitter Information

With each transition of the clock f

, the deviation from the reference clock f

is measured and input

voltage to the VCO is adjusted accordingly.The adjustment is done continuously with no abrupt changes

in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the

control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as

illustrated in

Figure A-5. Jitter Deﬁnitions

The relative deviation of t

is at its maximum for one clock period, and decreases towards zero for larger

number of clock periods (N).

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor