EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 831

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.11.1 Low-Voltage Interrupt (LVI)
In FPM, VREG_3V3 monitors the input voltage V
status bit LVDS is set to 1. On the other hand, LVDS is reset to 0 when V
interrupt, indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable
bit LVIE = 1.
23.4.11.2 HTI - High Temperature Interrupt
In FPM VREG monitors the die temperature T
HTDS is set to 1. Vice versa, HTDS is reset to 0 when T
by flag HTIF=1, is triggered by any change of the status bit HTDS if interrupt enable bit HTIE=1.
23.4.11.3 Autonomous Periodical Interrupt (API)
As soon as the configured timeout period of the API has elapsed, the APIF bit is set. An interrupt, indicated
by flag APIF = 1, is triggered if interrupt enable bit APIE = 1.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
On entering the Reduced Power Mode, the LVIF is not cleared by the
VREG_3V3.
On entering the Reduced Power Mode the HTIF is not cleared by the VREG.
Autonomous periodical interrupt (API)
High Temperature Interrupt (HTI)
Low-voltage interrupt (LVI)
Interrupt Source
MC9S12XE-Family Reference Manual Rev. 1.23
Table 23-13. Interrupt Vectors
DIE
NOTE
NOTE
. Whenever T
DDA
LVIE = 1; available only in Full Performance
available only in Full Performance Mode
. Whenever V
DIE
get below level T
Local Enable
DIE
APIE = 1
HTIE=1;
Chapter 23 Voltage Regulator (S12VREGL3V3V1)
Mode
exceeds level T
DDA
DDA
drops below level V
HTID
rises above level V
. An interrupt, indicated
HTIA
the status bit
LVIA,
LVID
the
. An
831