EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 363

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Refer to
2. Refer to
10.3.1.2
The XGATE Channel ID Register
currently active. This register will read “$00” if the XGATE module is idle. In debug mode this register
can be used to start and terminate threads. Refer to
information.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
XGSWEF
XGFACT
XGSS
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
XGIE
4
3
1
0
Section 10.6.1, “Debug
Section 10.4.5, “Software Error Detection”
XGATE Single Step — This bit forces the execution of a single instruction.
Read:
0 No single step in progress
1 Single step in progress
Write
0 No effect
1 Execute a single RISC instruction
Note: Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has
Fake XGATE Activity — This bit forces the XGATE to flag activity to the MCU even when it is idle. When it is set
the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE
idle periods
Read:
0 XGATE will only flag activity if it is not idle or in debug mode.
1 XGATE will always signal activity to the MCU.
Write:
0 Only flag activity if not idle or in debug mode.
1 Always signal XGATE activity.
XGATE Software Error Flag — This bit signals a software error. It is set whenever the RISC core detects an
error condition
and cause the XGATE to become idle.
Read:
0 No software error detected
1 Software error detected
Write:
0 No effect
1 Clears the XGSWEF bit
XGATE Interrupt Enable — This bit acts as a global interrupt enable for the XGATE module
Read:
0 All outgoing XGATE interrupts disabled (except software error interrupts)
1 All outgoing XGATE interrupts enabled
Write:
0 Disable all outgoing XGATE interrupts (except software error interrupts)
1 Enable all outgoing XGATE interrupts
XGATE Channel ID Register (XGCHID)
been executed.
(2)
Table 10-2. XGMCTL Field Descriptions (Sheet 3 of 3)
. The RISC core is stopped while this bit is set. Clearing this bit will terminate the current thread
Features”
MC9S12XE-Family Reference Manual Rev. 1.23
(Figure
10-4) shows the identifier of the XGATE channel that is
Section 10.6.1, “Debug Features”
Description
(1)
Chapter 10 XGATE (S12XGATEV3)
for further
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