EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 752

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Chapter 20 Serial Communication Interface (S12SCIV5)

To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and

To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10.

summarizes the results of the stop bit samples.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers

indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010

The RT8, RT9, and RT10 samples do not affect start bit veriﬁcation. If any

or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a

successful start bit veriﬁcation, the noise ﬂag (NF) is set and the receiver

assumes that the bit is a start bit (logic 0).

RT8, RT9, and RT10 Samples

summarizes the results of the data bit samples.

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 20-18. Data Bit Recovery

Table 20-19. Stop Bit Recovery

Data Bit Determination

Framing Error Flag

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