EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 463

BOARD EVAL FOR MC9S12XEP100

EVB9S12XEP100

Manufacturer Part Number
EVB9S12XEP100
Description
BOARD EVAL FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of EVB9S12XEP100

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
10.8.6
Table 10-24
Freescale Semiconductor
Return to Scheduler and Others
Semaphore Instructions
Single Register Instructions
Special Move instructions
Shift instructions Dyadic
Shift instructions immediate
Logical Triadic
Arithmetic Triadic
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
BRK
NOP
RTS
SIF
CSEM IMM3
CSEM RS
SSEM IMM3
SSEM RS
SEX RD
PAR RD
JAL RD
SIF RS
TFR RD,CCR
TFR CCR,RS
TFR RD,PC
BFFO RD, RS
ASR RD, RS
CSL RD, RS
CSR RD, RS
LSL RD, RS
LSR RD, RS
ROL RD, RS
ROR RD, RS
ASR RD, #IMM4
CSL RD, #IMM4
CSR RD, #IMM4
LSL RD, #IMM4
LSR RD, #IMM4
ROL RD, #IMM4
ROR RD, #IMM4
AND RD, RS1, RS2
OR RD, RS1, RS2
XNOR RD, RS1, RS2
SUB RD, RS1, RS2
SBC RD, RS1, RS2
ADD RD, RS1, RS2
ADC RD, RS1, RS2
Instruction Coding
summarizes all XGATE instructions in the order of their machine coding.
Functionality
Table 10-24. Instruction Set Summary (Sheet 1 of 3)
MC9S12XE-Family Reference Manual Rev. 1.23
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
10
0
0
0
0
IMM3
IMM3
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RD
RS
RS
RS
RS
9
0
0
1
1
For compare use SUB R0,Rs1,Rs2
8
0
1
0
1
7
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
RS1
RS1
RS1
RS1
RS1
RS1
RS1
RS
RS
RS
RS
RS
RS
RS
RS
6
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
IMM4
IMM4
IMM4
IMM4
IMM4
IMM4
IMM4
Chapter 10 XGATE (S12XGATEV3)
5
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
RS2
RS2
RS2
RS2
RS2
RS2
RS2
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
2
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
1
1
463
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1

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