EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 146

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

1. Read: Anytime.

Chapter 2 Port Integration Module (S12XEPIMV1)

Address 0x025F

Address 0x0260

Write: Anytime.

Port P interrupt ﬂag—

Each ﬂag is set by an active edge on the associated input pin. This could be a rising or a falling edge based on the

state of the PPSP register. To clear this ﬂag, write logic level 1 to the corresponding bit in the PIFP register. Writing

a 0 has no effect.

1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).

0 No active edge pending.

Port P Interrupt Flag Register (PIFP)

Port H Data Register (PTH)

Figure 2-50. Port P Interrupt Flag Register (PIFP)

Table 2-48. PPSP Register Field Descriptions

MC9S12XE-Family Reference Manual , Rev. 1.23

Figure 2-51. Port H Data Register (PTH)

Access: User read/write

Freescale Semiconductor