EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 753

BOARD EVAL FOR MC9S12XEP100

EVB9S12XEP100

Manufacturer Part Number
EVB9S12XEP100
Description
BOARD EVAL FOR MC9S12XEP100
Manufacturer
Freescale Semiconductor
Type
MCUr
Datasheet

Specifications of EVB9S12XEP100

Contents
Module and Misc Hardware
Processor To Be Evaluated
MC9S12XEP100
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
S12
Core Sub-architecture
S12
Silicon Core Number
MC9S12
Silicon Family Name
S12XE
Rohs Compliant
Yes
For Use With/related Products
MC9S12XEP100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
In
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag
is not set because the noise occurred before the start bit was found.
In
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Figure 20-22
Figure
RT Clock Count
Reset RT Clock
RT Clock Count
Reset RT Clock
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
RT Clock
RT Clock
Samples
Samples
20-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
RXD
RXD
the verification samples RT3 and RT5 determine that the first low detected was noise and
1
1
1
1
1
1
1
0
1
MC9S12XE-Family Reference Manual Rev. 1.23
Figure 20-22. Start Bit Search Example 1
Figure 20-23. Start Bit Search Example 2
0
1
1
1
1
0
0
Perceived Start Bit
0
0
0
0
0
0
Actual Start Bit
Chapter 20 Serial Communication Interface (S12SCIV5)
Start Bit
0
0
0
0
LSB
LSB
753

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