EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 685

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.0.4
Read: Anytime
Write: Anytime
18.3.0.5
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0003
Module Base + 0x0004
PMUX[3:0]
PINTE[3:0]
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
Reset
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
Field
3:0
3:0
W
W
R
R
PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to
micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is switched to the other micro time
base immediately.
0 The corresponding 16-bit timer counts with micro time base 0.
1 The corresponding 16-bit timer counts with micro time base 1.
PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request
whenever the time-out flag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)
enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF flag has to be
cleared first.
0 Interrupt of the corresponding PIT channel is disabled.
1 Interrupt of the corresponding PIT channel is enabled.
PIT Multiplex Register (PITMUX)
PIT Interrupt Enable Register (PITINTE)
0
0
0
0
7
7
0
0
0
0
6
6
Figure 18-7. PIT Interrupt Enable Register (PITINTE)
Figure 18-6. PIT Multiplex Register (PITMUX)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 18-6. PITINTE Field Descriptions
Table 18-5. PITMUX Field Descriptions
5
0
0
5
0
0
0
0
0
0
4
4
Description
Description
PINTE3
PMUX3
0
0
3
3
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
PMUX2
PINTE2
2
0
2
0
PINTE1
PMUX1
0
0
1
1
PINTE0
PMUX0
0
0
0
0
685