EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 1264

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Appendix C PCB Layout Guidelines

PCB Layout Guidelines

The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the

MCU itself. The following rules must be observed:

Example layouts are illustrated on the following pages.

Every supply pair must be decoupled by a ceramic capacitor connected as near as possible to the

corresponding pins .

Central point of the ground star should be the VSS3 pin.

Use low ohmic low inductance connections between VSS1, VSS2 and VSS3.

VSSPLL must be directly connected to VSS3.

Keep traces of VSSPLL, EXTAL, and XTAL as short as possible and occupied board area for C7,

C8, and Q1 as small as possible.

Do not place other signals or supplies underneath area occupied by C7, C8, and Q1 and the

connection area to the MCU.

Central power input should be fed in at the VDDA/VSSA pins.

MC9S12XE-Family Reference Manual , Rev. 1.23

Freescale Semiconductor