EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 849

Manufacturer Part Number

EVB9S12XEP100

BOARD EVAL FOR MC9S12XEP100

Manufacturer

Freescale Semiconductor

Module and Misc Hardware

Processor To Be Evaluated

MC9S12XEP100

Data Bus Width

Interface Type

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Rohs Compliant

For Use With/related Products

MC9S12XEP100

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array

read access from the CPU or XGATE.

CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not

Freescale Semiconductor

Offset Module Base + 0x0004

ECC Error Register Index— The ECCRIX bits are used to select which word of the FECCR register array is

being read. See

Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command

has completed.

0 Command complete interrupt disabled

1 An interrupt will be requested whenever the CCIF ﬂag in the FSTAT register is set (see

Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see

0 All single bit faults detected during array reads are reported

1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be

Flash Conﬁguration Register (FCNFG)

= Unimplemented or Reserved

Section 24.3.2.13, “Flash ECC Error Results Register

Figure 24-9. Flash Conﬁguration Register (FCNFG)

MC9S12XE-Family Reference Manual , Rev. 1.23

Table 24-14. FECCRIX Field Descriptions

Table 24-15. FCNFG Field Descriptions

Chapter 24 128 KByte Flash Module (S12XFTM128K2V1)

(FECCR),” for more details.