EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 355

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 10
XGATE (S12XGATEV3)
10.1
The XGATE module is a peripheral co-processor that allows autonomous data transfers between the
MCU’s peripherals and the internal memories. It has a built in RISC core that is able to pre-process the
transferred data and perform complex communication protocols.
The XGATE module is intended to increase the MCU’s data throughput by lowering the S12X_CPU’s
interrupt load.
Figure 10-1
This document describes the functionality of the XGATE module, including:
10.1.1
XGATE Request
XGATE Channel
Freescale Semiconductor
Revision
Number
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
V03.22
V03.23
V03.24
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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XGATE registers
XGATE RISC core
Hardware semaphores
Interrupt handling
Debug features
Security
Instruction set
A service request from a peripheral module which is directed to the XGATE by the S12X_INT
module (see
priority level.
The resources in the XGATE module (i.e. Channel ID number, Priority level, Service Request
Vector, Interrupt Flag) which are associated with a particular XGATE Request.
Introduction
Revision Date
Glossary of Terms
gives an overview on the XGATE architecture.
14 Dec 2005
06 Oct 2005
17 Jan 2006
(Section 10.7,
Figure
(Section 10.8, “Instruction
(Section 10.6, “Debug
(Section 10.3, “Memory Map and Register
(Section 10.5,
10.9.2/10-465
10-1). Each XGATE request attempts to activate a XGATE channel at a certain
(Section 10.4.1, “XGATE RISC
Sections
Affected
(Section 10.4.4,
“Security”)
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 10-1. Revision History
“Interrupts”)
- Internal updates
- Updated code example
- Internal updates
Mode”)
“Semaphores”)
Set”)
Description of Changes
Core”)
Definition”)
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