EVB9S12XEP100 Freescale Semiconductor, EVB9S12XEP100 Datasheet - Page 391

• Manufacturer Part Number: EVB9S12XEP100
• Description: BOARD EVAL FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of EVB9S12XEP100

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC
Operation
RS1 + RS2 + C ⇒ RD
Adds the content of register RS1, the content of register RS2 and the value of the Carry bit using binary
addition and stores the result in the destination register RD. The Zero Flag is also carried forward from the
previous operation allowing 32 and more bit additions.
Example:
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
ADC RD, RS1, RS2
N
∆
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000 and Z was set before this operation; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS1[15] & RS2[15] & RD[15]
Set if there is a carry from bit 15 of the result; cleared otherwise.
RS1[15] & RS2[15] | RS1[15] & RD[15]
Z
∆
ADD
ADC
BCC
V
∆
Source Form
C
∆
R6,R2,R2
R7,R3,R3 ; R7:R6 = R5:R4 + R3:R2
new
; conditional branch on 32 bit addition
MC9S12XE-Family Reference Manual Rev. 1.23
| RS1[15] & RS2[15] & RD[15]
Address
Mode
new
TRI
| RS2[15] & RD[15]
Add with Carry
0
0
0
1
new
new
1
Machine Code
RD
RS1
Chapter 10 XGATE (S12XGATEV3)
RS2
ADC
1
1
Cycles
P
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