MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1092

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MPC562/MPC564 Compression Features
A.2.4
During the compression process, compressed instructions change their location in the memory and are not
word aligned. Displacement fields in the direct branch instructions have to be updated by the compression
tool to make compressed instruction addressing possible. Four LSB bits of the displacement immediate
field (LI or BD) in the compressed direct branch instructions are used for bit addressing in the 32-bit
memory word. The remaining bits of the fields are used in the branch target calculation of the base address
(word address). The RCPU branch unit copies the bit pointer into the IP field of issued compressed branch
target address. The branch compressed target base address is calculated according the direct branch
addressing mode.
If a branch has absolute addressing mode, the branch target base address is calculated as a sign extension
of the base address portion of the LI (or BD) field.
If a branch has relative addressing mode, the branch target base address is calculated as a sum of the base
address of the branch and sign extended base address portion of the branch LI (or BD) field.
Figure A-3
address for the unconditional branch has 20 bits This yields an unconditional branch displacement limit of
4 Mbytes. The word pointer for the conditional branch has 10 bits. This yields a conditional branch
displacement limit of 4 Kbytes.
A-4
illustrates direct branch target address generation in “Decompression On” mode. The base
Compressed Address Generation with Direct Branches
Compressed
Instruction
Adddress
Memory
Layout
– Compressed Instruction
Figure A-2. Addressing Instructions with Compressed Address
x+4
x+c
x+8
x
MPC561/MPC563 Reference Manual, Rev. 1.2
Base Address
2*IP Bits
Freescale Semiconductor
27
IP
31