MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 844

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Time Processor Unit 3
19.4.4
19-14
SRESET
SRESET
13:15
Bits
0:7
10
11
12
8
9
Field
Addr
Field
Addr
TPU3 Interrupt Configuration Register (TICR)
MSB
MSB
0
Name
PCBK
CHBK
SRBK
BKPT
TPUF
0
—
—
1
1
Reserved
Breakpoint asserted flag. If an internal breakpoint caused the TPU3 to enter the halted state, the
TPU3 asserts the BKPT signal on the IMB and sets the BKPT flag. BKPT remains set until the
TPU3 recognizes a breakpoint acknowledge cycle, or until the IMB FREEZE signal is asserted.
Microprogram Counter (µPC) breakpoint flag. PCBK is asserted if a breakpoint occurs because
of a µPC register match with the µPC breakpoint register. PCBK is negated when the BKPT flag
is cleared.
Channel register breakpoint flag. CHBK is asserted if a breakpoint occurs because of a CHAN
register match with the CHAN register breakpoint register. CHBK is negated when the BKPT flag
is cleared.
Service request breakpoint flag. SRBK is asserted if a breakpoint occurs because of any of the
service request latches being asserted along with their corresponding enable flag in the
development support control register. SRBK is negated when the BKPT flag is cleared.
TPU3 FREEZE flag. TPUF is set whenever the TPU3 is in a halted state as a result of FREEZE
being asserted. This flag is automatically negated when the TPU3 exits the halted state because
of FREEZE being negated.
Reserved
Figure 19-7. DSSR — Development Support Status Register
Figure 19-8. TICR — TPU3 Interrupt Configuration Register
2
—
2
3
3
—
MPC561/MPC563 Reference Manual, Rev. 1.2
4
Table 19-9. DSSR Bit Descriptions
4
0x30 4006 (TPU_A), 0x30 4406 (TPU_B)
0x30 4008 (TPU_A), 0x30 4408 (TPU_B)
5
5
6
CIRL
0000_0000_0000_0000
0000_0000_0000_0000
6
7
7
BKPT PCBK CHBK SRBK TPUF
8
Description
8
ILBS
9
9
10
10
11
11
12
12
Freescale Semiconductor
—
13
13
—
14
14
LSB
LSB
15
15