MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 204

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Central Processing Unit
For data breakpoint exceptions, the register shown in
Execution resumes at offset from the base address indicated by MSR[IP] as follows:
3.15.5
In general, the architecture permits instructions to be partially executed when an alignment or data storage
interrupt occurs. In the core, instructions are not executed at all if an alignment interrupt condition is
3-60
•
•
•
•
1
0x01C00 – For data breakpoint match
0x01D00 – For instruction breakpoint match
0x01E00 – For development port maskable request or a peripheral breakpoint
0x01F00 – For development port non-maskable request
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain
the instruction address in compressed format.
Machine State Register (MSR)
Partially Executed Instructions
Register Name
Register Name
BAR
Table 3-37. Register Settings Following a Debug Exception
Table 3-38. Register Settings for Data Breakpoint Match
MPC561/MPC563 Reference Manual, Rev. 1.2
1
DCMPE
10:15
Other
Other
Bits
Bits
ME
1:4
LE
All
IP
N
Set to the effective address of the data access as computed by
the instruction that caused the interrupt
For I-breakpoints, set to the effective address of the instruction
that caused the interrupt. For L-breakpoint, set to the effective
address of the instruction following the instruction that caused
the interrupt. For development port maskable request or a
peripheral breakpoint, set to the effective address of the
instruction that the processor would have executed next if no
interrupt conditions were present. If the development port
request is asserted at reset, the value of SRR0 is undefined.
Cleared to 0
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[
If the development port request is asserted at reset, the value
of SRR1 is undefined.
No change
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
Table 3-38
is set.
Description
Description
RI]
.
Freescale Semiconductor