MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 8
MPC564MZP56
Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
MPC564MZP56
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Quantity:
364
Company:
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MPC564MZP56
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MPC564MZP56
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4.5.1
4.5.1.1
4.5.1.2
4.5.1.3
4.6
4.6.1
4.6.1.1
4.6.1.2
4.6.2
4.6.2.1
4.6.2.2
4.6.2.3
4.6.2.4
4.6.2.5
4.6.3
5.1
5.1.1
6.1
6.1.1
6.1.1.1
6.1.1.2
6.1.2
6.1.2.1
6.1.2.2
6.1.3
6.1.4
6.1.4.1
6.1.4.2
6.1.4.3
6.1.4.4
6.1.4.4.1
6.1.4.4.2
Freescale Semiconductor
Paragraph
Number
BBC Programming Model ............................................................................................ 4-17
Memory Map and Registers ............................................................................................ 5-2
System Configuration and Protection Features .............................................................. 6-3
BTB Operation .......................................................................................................... 4-14
Address Map ............................................................................................................. 4-17
BBC Register Descriptions ....................................................................................... 4-19
Decompressor Class Configuration Registers .......................................................... 4-25
USIU Special-Purpose Registers ................................................................................ 5-6
System Configuration ................................................................................................. 6-3
External Master Modes ............................................................................................... 6-4
USIU General-Purpose I/O ......................................................................................... 6-6
Enhanced Interrupt Controller .................................................................................... 6-8
BTB Invalidation .................................................................................................. 4-16
BTB Enabling/Disabling ...................................................................................... 4-16
BTB Inhibit Regions ............................................................................................. 4-16
BBC Special Purpose Registers (SPRs) ............................................................... 4-17
DECRAM and DCCR Block ................................................................................ 4-18
BBC Module Configuration Register (BBCMCR) ............................................... 4-19
Region Base Address Registers (MI_RBA[0:3]) ................................................. 4-21
Region Attribute Registers (MI_RA[0:3]) ............................................................ 4-22
Global Region Attribute Register (MI_GRA) ...................................................... 4-23
External Interrupt Relocation Table Base Address Register (EIBADR) .............. 4-25
USIU Pin Multiplexing ........................................................................................... 6-4
Arbitration Support ................................................................................................. 6-4
Operation in External Master Modes ...................................................................... 6-5
Address Decoding for External Accesses ............................................................... 6-6
Key Features ........................................................................................................... 6-8
Interrupt Configuration ........................................................................................... 6-8
Regular Interrupt Controller Operation (MPC555/MPC556-Compatible Mode) 6-10
Enhanced Interrupt Controller Operation ............................................................. 6-11
Lower Priority Request Masking ...................................................................... 6-14
Backward Compatibility with MPC555/MPC556 ............................................ 6-14
Unified System Interface Unit (USIU) Overview
System Configuration and Protection
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 5
Chapter 6
Title
Number
Page
viii
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