MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 224

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Burst Buffer Controller 2 Module
All the above registers may be accessed in the supervisor mode only. An exception is internally generated
by the RCPU if there is an attempt to access them in user mode. An external master receives a transfer
error acknowledge when attempting to access a register in user mode.
4.6.1.2
The DECRAM occupies addresses from 0x2F 8000 to 0x2F 87FF. The DCCR block occupies addresses
from 0x2F A000 to 0x2F A03F.
The address for non-implemented memory blocks is not acknowledged, and causes an error condition.
4-18
SPR Number
(Decimal)
784
785
786
787
816
817
818
819
DECRAM and DCCR Block
If one of these registers is written within 4 instructions of a branch target,
the user application may crash. To prevent this, ensure that any instruction
writing to these registers is preceded by 4 instructions that are not the target
of any branch, and is followed by an isync instruction.
Access (Hex)
Address for
External
0x2180
0x2380
0x2580
0x2780
0x2190
0x2390
0x2590
0x2790
Master
IMPU Region Base Address Register 0 (MI_RBA0). See
descriptions.
IMPU Region Base Address Register 1 (MI_RBA1). See
descriptions.
IMPU Region Base Address Register 2 (MI_RBA2). See
descriptions.
IMPU Region Base Address Register 3 (MI_RBA3). See
descriptions.
IMPU Region Attribute Register 0 (MI_RA0). See
IMPU Region Attribute Register 1 (MI_RA1). See
IMPU Region Attribute Register 2 (MI_RA2). See
IMPU Region Attribute Register 3 (MI_RA3). See
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 4-3. BBC SPRs (continued)
NOTE
Register Name
Table 4-6
Table 4-6
Table 4-6
Table 4-6
Table 4-5
Table 4-5
Table 4-5
Table 4-5
for bits descriptions.
for bits descriptions.
for bits descriptions.
for bits descriptions.
Freescale Semiconductor
for bits
for bits
for bits
for bits