MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 13

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

9.5.12
9.5.13
9.5.14
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
10.2.6.1
10.2.6.2
10.2.6.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.4
10.5
10.6
10.7
10.8
10.9
10.9.1
10.9.2
10.9.3
10.9.4
10.9.5
10.9.6
Freescale Semiconductor
Paragraph
Number
Overview ....................................................................................................................... 10-1
Memory Controller Architecture .................................................................................. 10-3
Chip-Select Timing ..................................................................................................... 10-10
Write and Byte Enable Signals ................................................................................... 10-24
Dual Mapping of the Internal Flash EEPROM Array ................................................ 10-24
Dual Mapping of an External Flash Region ............................................................... 10-26
Global (Boot) Chip-Select Operation ......................................................................... 10-27
Memory Controller External Master Support ............................................................. 10-28
Programming Model ................................................................................................... 10-31
Bus Operation in External Master Modes ................................................................. 9-49
Contention Resolution on External Bus .................................................................... 9-53
Show Cycle Transactions .......................................................................................... 9-55
Associated Registers ................................................................................................. 10-4
Port Size Configuration ............................................................................................ 10-4
Write-Protect Configuration ..................................................................................... 10-5
Address and Address Space Checking ...................................................................... 10-5
Burst Support ............................................................................................................ 10-5
Reduced Data Setup Time ........................................................................................ 10-6
Memory Devices Interface Example ...................................................................... 10-12
Peripheral Devices Interface Example .................................................................... 10-13
Relaxed Timing Examples ...................................................................................... 10-14
Extended Hold Time on Read Accesses ................................................................. 10-18
Summary of GPCM Timing Options ...................................................................... 10-22
General Memory Controller Programming Notes .................................................. 10-31
Memory Controller Status Registers (MSTAT) ..................................................... 10-32
Memory Controller Base Registers (BR0–BR3) .................................................... 10-32
Memory Controller Option Registers (OR0–OR3) ................................................ 10-34
Dual-Mapping Base Register (DMBR) .................................................................. 10-36
Dual-Mapping Option Register (DMOR) ............................................................... 10-37
Case 1: Normal Setup Time .................................................................................. 10-6
Case 2: Short Setup Time ..................................................................................... 10-7
Summary of Short Setup Time ............................................................................. 10-8
MPC561/MPC563 Reference Manual, Rev. 1.2
Memory Controller
Contents
Chapter 10
Title
Number
Page
xiii