MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1160

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

TPU3 ROM Functions
D-8
0
ADDRESS OFFSETS
1
0x30XXWC
0x30XXWA
0x30XXWE
0x30XXW0
0x30XXW2
0x30XXW4
0x30XXW6
0x30XXW8
2
0
0
0
3
1
1
1
0
0
= Written By RCPU
= Written By TPU
Channel Function Select
Host Sequence
Host Service Request
Channel Priority
Channel Interrupt Enable
Channel Interrupt Status
NAME
0
TABLE_SIZE
Figure D-4. TSM Parameters — Master Mode
1
MPC561/MPC563 Reference Manual, Rev. 1.2
2
3
xxxx – TSM Function Number. Assigned
during microcode assembly. See
x0 – Local Mode Acceleration Table
x1 – Split Mode Acceleration Table
0x – Rotate Pin_Sequence Once Between Steps
1x – Rotate Pin_Sequence Twice Between Steps
00 – No Host Service (Reset Condition)
01 – Initialize, Pin Low
10 – Initialize, Pin High
11 – Move Request (Master Only)
00 – Disabled
01 – Low Priority
10 – Medium Priority
11 – High Priority
0 – Channel Interrupt Disabled
1 – Channel Interrupt Enabled
0 – Channel Interrupt Not Asserted
1 – Channel Interrupt Asserted
4
PARAMETER RAM
CONTROL BITS
= Written by RCPU and TPU
= Unused Parameters
CHANNEL_COUNTER
5
CURRENT_POSITION
DESIRED_POSITION
START_PERIOD
SLEW_PERIOD
PIN_SEQUENCE
6
7
OPTIONS
BITS
8
9
10 11 12
Table D-1
TABLE_INDEX
W = Channel Number
For address offsets: XX=41 for
TPU_A, 45 for TPU_B
YY=40 for TPU_A, 44
for TPU_B
See
PRAM Address Offset Map.
Table 19-24
13
0x30YY1C – 0x30YY1E
0x30YY0C – 0x30YY12
0x30YY18 – 0x30YY1A
0x30YY14 – 0x30YY16
14
ADDRESSES
Freescale Semiconductor
0x30YY0A
0x30YY20
15
S
A
for the
Param 0
Param 1
Param 2
Param 3
Param 4
Param 5
Param 6
Param 7