MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 676

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Queued Serial Multi-Channel Module
RDRF must be cleared before the next transfer from the shifter can take place. If RDRF is set when the
shifter is full, transfers are inhibited and the overrun error (OR) flag in SCxSR is set. OR indicates that the
RDRx needs to be serviced faster. When OR is set, the data in the RDRx is preserved, but the data in the
serial shifter is lost.
When a completed frame is received into the RDRx, either the RDRF or OR flag is always set. If RIE in
SCCxR1 is set, an interrupt results whenever RDRF is set. The receiver status flags NF, FE, and PF are set
simultaneously with RDRF, as appropriate. These receiver flags are never set with OR because the flags
apply only to the data in the receive serial shifter. The receiver status flags do not have separate interrupt
enables, since they are set simultaneously with RDRF and must be read at the same time as RDRF.
When the CPU reads SCxSR and SCxDR in sequence, it acquires status and data, and also clears the status
flags. Reading SCxSR acquires status and arms the clearing mechanism. Reading SCxDR acquires data
and clears SCxSR.
15.7.7.9
Idle-Line Detection
During a typical serial transmission, frames are transmitted isochronically and no idle time occurs between
frames. Even when all the data bits in a frame are logic ones, the start bit provides one logic zero bit-time
during the frame. An idle line is a sequence of contiguous ones equal to the current frame size. Frame size
is determined by the state of the M bit in SCCxR1.
The SCI receiver has both short and long idle-line detection capability. Idle-line detection is always
enabled. The idle-line type (ILT) bit in SCCxR1 determines which type of detection is used. When an
idle-line condition is detected, the IDLE flag in SCxSR is set.
For short idle-line detection, the receiver bit processor counts contiguous logic one bit-times whenever
they occur. Short detection provides the earliest possible recognition of an idle-line condition, because the
stop bit and contiguous logic ones before and after it are counted. For long idle-line detection, the receiver
counts logic ones after the stop bit is received. Only a complete idle frame causes the IDLE flag to be set.
In some applications, software overhead can cause a bit-time of logic level one to occur between frames.
This bit-time does not affect content, but if it occurs after a frame of ones when short detection is enabled,
the receiver flags an idle line.
When the ILIE bit in SCCxR1 is set, an interrupt request is generated when the IDLE flag is set. The flag
is cleared by reading SCxSR and SCxDR in sequence. For receiver queue operation, IDLE is cleared when
SCxSR is read with IDLE set, followed by a read of SCRQ[0:15]. IDLE is not set again until after at least
one frame has been received (RDRF = 1). This prevents an extended idle interval from causing more than
one interrupt.
15.7.7.10 Receiver Wake-Up
The receiver wake-up function allows a transmitting device to direct a transmission to a single receiver or
to a group of receivers by sending an address frame at the start of a message. Hardware activates each
receiver in a system under certain conditions. Resident software must process address information and
enable or disable receiver operation.
MPC561/MPC563 Reference Manual, Rev. 1.2
15-58
Freescale Semiconductor