MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 18

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

14.4.4.2
14.4.4.3
14.4.4.3.1
14.4.4.3.2
14.4.4.3.3
14.4.4.3.4
14.4.4.4
14.4.4.4.1
14.4.4.4.2
14.4.4.4.3
14.4.4.4.4
14.4.5
14.4.6
14.4.7
14.4.7.1
14.4.7.2
14.5
14.5.1
14.5.2
14.6
14.6.1
14.6.2
14.6.3
14.6.3.1
14.6.4
14.6.5
14.6.5.1
14.6.5.2
14.6.5.3
14.6.5.4
15.1
15.2
15.2.1
15.3
15.4
15.4.1
15.4.2
Freescale Semiconductor
Paragraph
Number
Trigger and Queue Interaction Examples ................................................................... 14-53
QADC64E Integration Requirements ......................................................................... 14-65
Block Diagram .............................................................................................................. 15-1
Key Features ................................................................................................................. 15-2
Memory Maps ............................................................................................................... 15-4
QSMCM Global Registers ............................................................................................ 15-6
QADC64E Clock (QCLK) Generation ................................................................... 14-48
Periodic/Interval Timer ........................................................................................... 14-50
Configuration and Control Using the IMB3 Interface ............................................ 14-51
Queue Priority Schemes .......................................................................................... 14-53
Conversion Timing Schemes .................................................................................. 14-62
Port Digital Input/Output Signals ........................................................................... 14-65
External Trigger Input Signals ................................................................................ 14-66
Analog Power Signals ............................................................................................. 14-66
Analog Reference Signals ....................................................................................... 14-69
Analog Input Signals .............................................................................................. 14-70
MPC561/MPC563 QSMCM Details ........................................................................ 15-3
Low-Power Stop Operation ...................................................................................... 15-6
Freeze Operation ....................................................................................................... 15-6
Reserved Mode ................................................................................................... 14-42
Single-Scan Modes ............................................................................................. 14-43
Continuous-Scan Modes ..................................................................................... 14-45
QADC64E Bus Interface Unit ............................................................................ 14-51
QADC64E Bus Accessing .................................................................................. 14-51
Analog Supply Filtering and Grounding ............................................................ 14-67
Analog Input Considerations .............................................................................. 14-71
Settling Time for the External Circuit ................................................................ 14-73
Error Resulting from Leakage ............................................................................ 14-73
Accommodating Positive/Negative Stress Conditions ....................................... 14-74
Software Initiated Single-Scan Mode ............................................................. 14-43
External Trigger Single-Scan Mode ............................................................... 14-44
External Gated Single-Scan Mode ................................................................. 14-44
Periodic/Interval Timer Single-Scan Mode .................................................... 14-45
Software Initiated Continuous-Scan Mode ..................................................... 14-46
External Trigger Continuous-Scan Mode ....................................................... 14-47
External Gated Continuous-Scan Mode ......................................................... 14-47
Periodic/Interval Timer Continuous-Scan Mode ............................................ 14-48
Queued Serial Multi-Channel Module
MPC561/MPC563 Reference Manual, Rev. 1.2
Contents
Chapter 15
Title
Number
Page
xviii