MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 319

IC MCU 512K FLASH 56MHZ 388-BGA

MPC564MZP56

Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheets

Specifications of MPC564MZP56

Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available

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Table 8-6
8.7.2
Table 8-5
8.7.3
Exiting from low-power modes occurs through an asynchronous interrupt or a synchronous interrupt
generated by the interrupt controller. Any enabled asynchronous interrupt clears the LPM bits but does not
change the PLPRCR[CSRC] bit.
Freescale Semiconductor
Normal-low (“gear”)
Operation Mode
summarizes the control bit settings for the different clock power modes.
describes the clock frequency and chip functionality for each power mode.
SRAM Standby
Normal-high
Power-down
Deep-sleep
Power Mode Descriptions
Exiting from Low-Power Modes
Doze-high
Doze-low
Sleep
Not active
Not active
Not active
Active
Active
Active
Active
Active
SPLL
Normal-low (“gear”)
Table 8-4. Power Mode Control Bit Settings
Power Mode
Normal-high
Power-down
Deep-sleep
MPC561/MPC563 Reference Manual, Rev. 1.2
Doze-high
Doze-low
Table 8-5. Power Mode Descriptions
Sleep
Full frequency ÷
Full frequency ÷
Full frequency ÷
Full frequency ÷
Not active
Not active
Not active
Not active
2
2
Clocks
2
2
DFNL+1
DFNL+1
DFNH
DFNH
LPM[0:1]
00
00
01
01
10
11
11
Full functions not in use
Enabled: RTC, PIT, TB
(RCPU, BBC, FPU)
Enabled: RTC, PIT,
Disabled: extended
CSRC
Functionality
TB and DEC,
SRAM data
are shut off
1
X
X
X
0
0
1
and DEC
controller
retention
core
TEXPS
X
X
X
X
X
1
0
VDD, QVDDL, NVDDL,
VDD, QVDDL, NVDDL,
Power Pins that Need
KAPWR, IRAMSTBY
KAPWR, IRAMSTBY
KAPWR, VDDSYN,
KAPWR, VDDSYN,
KAPWR, VDDSYN,
to be Powered-Up
IRAMSTBY
IRAMSTBY
IRAMSTBY
IRAMSTBY
Clocks and Power Control
All On
All On
8-17

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