MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 742
MPC564MZP56
Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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Modular Input/Output Subsystem (MIOS14)
17.3.3
The read/write and control bus (RWCB) allows read and write data transfers to and from any I/O
submodule through the MBISM. It includes signals for data and addresses as well as control signals. The
control signals allow 16-bit simple synchronous single master accesses and supports fast or slow master
accesses.
17.3.4
The request bus (RQB) provides interrupt request signals along with I/O submodule identification and
priority information to the MBISM.
17.3.5
The 16-bit counter bus set (CBS) is a set of six 16-bit counter buses. The CBS makes it possible to transfer
information between submodules. Typically, counter submodules drive the CBS, while action submodules
process the data on these buses. Note, however, that some submodules are self-contained and therefore
independent of the counter bus set.
17.4
The address space of the MIOS14 consist of 4 Kbytes starting at the base address of the module
(0x306000). The overall address map organization is shown in
All MIOS14 unimplemented locations within the addressable range, return a logic 0 when accessed. In
addition, the internal TEA (transfer error acknowledge) signal is asserted.
All unused bits within MIOS14 registers return a 0 when accessed.
17.4.1
A bus error signal is generated when access to an unimplemented or reserved 16-bit register is attempted,
or when a priviledge violation occurs. A bus error is generated under any of the following conditions:
17-10
•
•
•
•
•
•
•
The read/write and control bus
The request bus
The counter bus set
Attempted access to unimplemented 16-bit registers within the decoded register block boundary.
Attempted user access to supervisor registers
Attempted access to test registers when not in test mode
Attempted write to read-only registers
MIOS14 Programming Model
Read/Write and Control Bus
Request Bus
Counter Bus Set
Bus Error Support
Some submodules do not generate interrupts and are therefore independent
of the RQB.
MPC561/MPC563 Reference Manual, Rev. 1.2
NOTE
Figure
17-2.
Freescale Semiconductor
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