MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1350

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

66-MHz Electrical Characteristics
G.13 RESET Timing
Note: (V
G-44
49a
55a
43
44
45
46
47
48
49
50
51
52
53
54
55
DD
CLKOUT to HRESET high impedance
CLKOUT to SRESET high impedance
RSTCONF pulse width
Configuration Data to HRESET rising edge Setup Time
Configuration Data to RSTCONF rising edge set up time
Configuration Data hold time after RSTCONF negation
Configuration Data hold time after HRESET negation
RSTCONF hold time after HRESET negation
HRESET and RSTCONF asserted to Data out drive
RSTCONF negated to Data out high impedance
CLKOUT of last rising edge before chip tristates HRESET to Data out high impedance
DSDI, DSCK set up
DSDI, DSCK hold time
SRESET negated to CLKOUT rising edge for DSDI and DSCK sample
HRESET, SRESET, PORESET pulse width
= 2.6 V ± 0.1 V, V
EVTI
EVTI
RSTI
RSTI
DDH
= 5.0 V ± 0.25 V, T
Figure G-32. Disable Auxiliary From RSTI
Figure G-31. Enable Auxiliary From RSTI
MPC561/MPC563 Reference Manual, Rev. 1.2
Characteristic
Table G-14. RESET Timing
A
= T
2
1
L
to T
H
13
13
)
14
14
Min
231
231
257
121
100
24
25
25
25
46
—
—
0
0
0
Freescale Semiconductor
66 MHz
Max
20
20
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns