MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 1205

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

D.20 Serial Input/Output Port (SIOP)
The serial input/output port (SIOP) TPU3 function uses two or three TPU3 channels to form a uni- or
bidirectional synchronous serial port that can be used to communicate with a wide variety of devices. It
can be used to add serial capabilities to a device without a serial port, or to extend the capabilities of one
with a hardware-synchronous port. The SIOP TPU3 function has been designed to closely resemble the
SIOP hardware port found on some Freescale MCUs.
SIOP operates in master mode (the TPU3 always generates the clock) and has the following programmable
features:
When a transfer of data is complete, the SIOP function notifies the host RCPU by issuing an interrupt
request. The arrangement of the multiple SIOP channels is fixed: the data-out channel is the channel above
the clock channel and the data-in channel is the channel below the clock channel. In clock-only or
uni-directional mode, the unused TPU3 channels are free to run other TPU3 functions. Two possible SIOP
configurations are shown in
D.20.1
Figure D-32
sections describe these parameters.
Freescale Semiconductor
Da ta Out-Chan x+1
Clo c k Out-Chan x
Da ta Out-Cha n x+1
Da ta In-Cha n x-1
Clo c k Out-Chan x
1. Choice of one-channel clock-only, two-channel clock + transmit, two-channel clock + receive, or
2. Freely programmable baud-rate period over a 15-bit range of TCR1 counts
3. Selection of MSB or LSB first shift direction
4. Variable transfer size from 1 to 16 bits
5. Programmable clock polarity
three-channel clock + transmit + receive operating modes
Parameters
shows the host interface areas and parameter RAM for the SIOP function. The following
10-bit output only transfer, LSB first with data valid on clock falling edge
8-bit bidirectional transfer, MSB first with data valid on clock rising edge
Figure D-31
Figure D-31. Two Possible SIOP Configurations
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MPC561/MPC563 Reference Manual, Rev. 1.2
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TPU3 ROM Functions
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