MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 956

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Development Support
23-42
SRESET
SRESET
11:12
Field — RST CHSTP
Field — SEE
Addr
Bits
4:5
10
13
14
15
16
17
18
19
20
21
0
1
2
3
6
7
8
9
MSB
16
0
DTLBER
ITLBER
CHSTP
FPUVE
FPASE
Name
DECE
SYSE
MCE
EXTI
PRE
RST
SEE
ALE
TR
17
—
—
—
—
—
—
1
—
18
2
Reserved
Reset interrupt bit. This bit is set when the system reset pin is asserted.
Checkstop bit. Set when the processor enters checkstop state.
Machine check interrupt bit. Set when a machine check exception (other than one caused by a
data storage or instruction storage error) is asserted.
Reserved
External interrupt bit. Set when the external interrupt is asserted.
Alignment exception bit. Set when the alignment exception is asserted.
Program exception bit. Set when the program exception is asserted.
Floating point unavailable exception bit. Set when the program exception is asserted.
Decrementer exception bit. Set when the decrementer exception is asserted.
Reserved
System call exception bit. Set when the system call exception is asserted.
Trace exception bit. Set when in single-step mode or when in branch trace mode.
Floating point assist exception bit. Set when the floating point assist exception occurs.
Reserved
Software emulation exception. Set when the software emulation exception is asserted.
Reserved
Implementation specific instruction protection error
This bit is set as a result of an instruction protection error. Results in debug mode entry if debug
mode is enabled and the corresponding enable bit is set.
Reserved
Implementation specific data protection error
This bit is set as a result of an data protection error. Results in debug mode entry if debug mode
is enabled and the corresponding enable bit is set.
ITLBER —
MCE
19
3
Figure 23-16. Exception Cause Register (ECR)
MPC561/MPC563 Reference Manual, Rev. 1.2
20
4
Table 23-18. ECR Bit Descriptions
DTLBER
—
21
5
0000_0000_0000_0000
0000_0000_0000_0000
EXTI ALE PRE FPUVE DECE
22
6
SPR 148
23
7
Description
24
8
—
25
9
10
26
11
27
LBRK IBRK EBRK
—
12
28
SYSE
Freescale Semiconductor
13
29
TR
14
30
FPASE
LSB
DPI
15
31