MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 416

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Memory Controller
Clock
Address
TS
No Effect, ACS = 00
TA
CS
RD/WR
WE/BE
OE
CSNT = 1
Data
Figure 10-14. Relaxed Timing — Write Access (ACS = 00, SCY = 0, CSNT = 1, TRLX = 1
10.3.4
Extended Hold Time on Read Accesses
For devices that require a long disconnection time from the data bus on read accesses, the bit EHTR in the
corresponding OR register can be set. In this case any MPC561/MPC563 access to the external bus
following a read access to the referred memory bank is delayed by one clock cycle unless it is a read access
to the same bank.
Figure 10-15
through
Figure 10-18
show the effect of the EHTR bit on memory
controller timing.
Figure 10-15
shows a write access following a read access. Because EHTR = 0, no extra clock cycle is
inserted between memory cycles.
MPC561/MPC563 Reference Manual, Rev. 1.2
10-18
Freescale Semiconductor