MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 521

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

The next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is
actively being serviced.
Situation S4
is saved, and as soon as queue 1 is finished, queue 2 servicing begins.
Situation S5
busy, the trigger overrun error bit is set, but queue 1 execution is not disturbed. Situation S5 also shows
that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is in
use in either queue.
Freescale Semiconductor
Q1
Q2
QS
Q1
Q2
QS
0000
IDLE
(Figure
(Figure
Q1:
IDLE
T1
0000
C1
13-31) shows that when multiple queue 2 trigger events are detected while queue 1 is
ACTIVE
IDLE
13-30) shows that a queue 2 trigger event that is recognized while queue 1 is active
TOR1 PF1
T1
1000
IDLE
C2
Q1:
T1
0100
C1
MPC561/MPC563 Reference Manual, Rev. 1.2
Q2:
Figure 13-29. CCW Priority Situation 3
Figure 13-30. CCW Priority Situation 4
1000
T2
C2
ACTIVE
PAUSE
Q2:
C1
ACTIVE
TOR2 PF2
T2
TRIGGERED
T2
0110
C3
C2
1011
C4
0101
CF1
T1
C1
C3
ACTIVE
TOR1 CF1
T1
1001
PAUSE
C2
ACTIVE
C4
0010
C3
0001
C4
CF2
T2
IDLE
C3
ACTIVE
TOR2
T2
0010
IDLE
C4
QADC64E Legacy Mode Operation
CF2
IDLE
0000
IDLE
0000
QADC S3
QADC S4
13-57