MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 170

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Central Processing Unit
3.9.10.2
The FPECR, SPR 1022, is a supervisor-level internal status and control register used by the user’s
floating-point assist software envelope. It contains four status bits that indicate whether the result of the
operation is tiny and whether any of three source operands are denormalized. In addition, it contains one
control bit to enable or disable SIE mode. This register must not be accessed by user code.
A listing of FPECR bit settings is shown in
3-26
SRESET
SRESET
Bits
1:27
28
29
30
31
0
Field SIE
Field
Addr
Floating-Point Exception Cause Register (FPECR)
MSB
Name
16
DNC
DNB
DNA
0
SIE
Software must insert a sync instruction before reading the FPECR.
TR
—
17
1
Figure 3-18. Floating-Point Exception Cause Register (FPECR)
Synchronized ignore exception mode control bit.
0 Disable SIE mode
1 Enable SIE mode
Reserved
Source operand C denormalized status bit.
0 Source operand C is not denormalized
1 Source operand C is denormalized
Source operand B denormalized status bit.
0 Source operand B is not denormalized
1 Source operand B is denormalized
Source operand A denormalized status bit.
0 Source operand A is not denormalized
1 Source operand A is denormalized
Floating-point tiny result.
0 Floating-point result is not tiny
1 Floating-point result is tiny
18
2
19
3
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-16. FPECR Bit Descriptions
20
4
21
5
Table
—
0000_0000_0000_0000
0000_0000_0000_0000
22
6
NOTE
3-16.
SPR 1022
23
7
Description
—
24
8
25
9
10
26
11
27
DNC DNB DNA
12
28
Freescale Semiconductor
13
29
14
30
LSB
TR
15
31