MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 927

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

These can be ignored only by the software that handles the breakpoints. The following figure illustrates
this partially supported scenario.
23.2.1.4
The CPU can be programmed to either recognize internal breakpoints only when the recoverable interrupt
bit in the MSR is set (masked mode) or it can be programmed to always recognize internal breakpoints
(non-masked mode).
When the CPU is programmed to recognize internal breakpoints only when MSR[RI] = 1, it is possible to
debug all parts of the code except when the machine status save/restore registers (SRR0 and SRR1), DAR
(data address register) and DSISR (data storage interrupt status register) are busy and, therefore, MSR[RI]
= 0, (in the prologues and epilogues of interrupt/exception handlers).
When the CPU is programmed always to recognize internal breakpoints, it is possible to debug all parts of
the code. However, if an internal breakpoint is recognized when MSR[RI] = 0 (SRR0 and SRR1 are busy),
the machine enters into a non-restartable state. For more information refer to
Freescale Semiconductor
•
A partially supported scenario:
— Looking for:
— Programming option:
— Result:
Data size: half-word
Address: greater than or equal 0x00000002 and less than 0x0000000e
Data value: greater than 0x4e204e20 and less than 0x9c409c40
One L-address comparator = 0x00000001 and program for greater than
One L-address comparator = 0x0000000e and program for less than
One L-data comparator = 0x4e204e20 and program for greater than
One L-data comparator = 0x9c409c40 and program for less than
Both byte masks = 0x0
Both L-data comparators program to half-word mode or to word mode
The event will be correctly detected if the compiler chooses a load/store instruction with data
size of half-word. If the compiler chooses load/store instructions with data size greater than
half-word (word, multiple), there might be some false detections.
Context Dependent Filter
Possible false detect on these half-words when using word/multiple
Figure 23-2. Partially Supported Watchpoint/Breakpoint Example
0x0000_0000
0x0000_0004
0x0000_0008
0x0000_000C
0x0000_0010
MPC561/MPC563 Reference Manual, Rev. 1.2
Section 3.13.4,
Development Support
“Exceptions.”
23-13