MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 359

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

External Bus Interface
In the MPC561/MPC563, no internal master initiates write bursts. The MPC561/MPC563 is designed to
perform this kind of transaction in order to support an external master that is using the memory controller
services. Refer to
Section 10.8, “Memory Controller External Master
Support.”
During the data phase of a burst-read cycle, the master receives data from the addressed slave. If the master
needs more than one data beat, it asserts BDIP. Upon receiving the second-to-last data beat, the master
negates BDIP. The slave stops driving new data after it receives the negation of the BDIP signal at the
rising edge of the clock.
Burst inputs (reads) in the MPC561/MPC563 are used only for instruction cycles. Data load cycles are not
supported.
Figures 9-12 through 9-21 are examples of various burst cycles, including illustrations of burst-read and
burst-write cycles for both the 16- and 32-bit port sizes.
MPC561/MPC563 Reference Manual, Rev. 1.2
Freescale Semiconductor
9-19