MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 602

• Manufacturer Part Number: MPC564MZP56
• Description: IC MCU 512K FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Core: PowerPC
• Processor Series: MPC5xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 56 MHz
• Data Ram Size: 32 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 32
• Height: 1.95 mm
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Length: 27 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 2.7 V, 5.25 V
• Supply Voltage (min): 2.5 V, 4.75 V
• Width: 27 mm
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

QADC64E Enhanced Mode Operation
The above situations cover normal overlap conditions that arise with asynchronous trigger events on the
two queues. An additional conflict to consider is that the freeze condition can arise while the QADC64E
is actively executing CCWs. The conventional use for the freeze mode is for software/hardware
debugging. When the CPU background debug mode is enabled and a breakpoint occurs, the freeze signal
is issued, which can cause peripheral modules to stop operation. When freeze is detected, the QADC64E
completes the conversion in progress, unlike queue 1 suspending queue 2. After the freeze condition is
removed, the QADC64E continues queue execution with the next CCW in sequence.
Trigger events that occur during freeze are not captured. When a trigger event is pending for queue 2 before
freeze begins, that trigger event is remembered when the freeze is passed. Similarly, when freeze occurs
while queue 2 is suspended, after freeze, queue 2 resumes execution as soon as queue 1 is finished.
Situations 12 through 19
14-60
Q1
Q2
QS
0000
IDLE
Q2:
IDLE
T2
C1
ACTIVE
0010
(Figure 14-36
C2
Q1:
Q1:
T1
SUSPEND
T1
TOR2
MPC561/MPC563 Reference Manual, Rev. 1.2
C1
Figure 14-35. CCW Priority Situation 11
ACTIVE
Figure 14-36. CCW Freeze Situation 12
T2
C1
1010
C2
C2
to
PF1
Figure
ACT
0110
C2
PF2
PAUSE
0101
FREEZE
PAUSE
14-43) show examples of all of the freeze situations.
T2
C3
ACTIVE
0110
C4
T1
SUSPEND
TOR2
C3
T2
ACTIVE
1010
C3
C4
CF1
C4
ACT
CF1
0010
C4
CF2
RESUME=1
IDLE
Freescale Semiconductor
QADC S12
IDLE
0000
QADC S11