MPC564MZP56 Freescale Semiconductor, MPC564MZP56 Datasheet - Page 307
MPC564MZP56
Manufacturer Part Number
MPC564MZP56
Description
IC MCU 512K FLASH 56MHZ 388-BGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Core
PowerPC
Processor Series
MPC5xx
Data Bus Width
32 bit
Maximum Clock Frequency
56 MHz
Data Ram Size
32 KB
On-chip Adc
Yes
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
32
Height
1.95 mm
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Length
27 mm
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
2.7 V, 5.25 V
Supply Voltage (min)
2.5 V, 4.75 V
Width
27 mm
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
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If limp mode is enabled (by the MODCK[1:3] pins), and PORESET is negated before the external
oscillator has started up, the backup clock, BUCLK, will be used to clock the device. The device will start
to run in limp mode. Software can then switch the clock mode from BUCLK to PLL. If an application
requires that the device always comes out of reset in normal mode, PORESET should be asserted long
enough for the external oscillator to start up. The maximum start-up time of an external oscillator is given
in
additional 100, 000 input clock cycles.
If limp mode is disabled at reset, a short reset of at least 3 µs is enough to obtain normal chip operation,
because the BUCLK will not start. The system will wait for the external oscillator to start-up and stabilize.
The PLL will begin to lock once PORESET has been negated, assuming stable KAPWR and VDDSYN
power supplies and internal oscillator (or external clock). The PLL maximum lock time is determined by
the input clock to the phase comparator. The PLL locks within 500 input clock cycles if the PLPRCR[MF]
<= 4. The PLL locks within 1000 input clock cycles if PLPRCR[MF] >4. HRESET will be released 512
system clock cycles after the PLL locks.
Whenever PORESET is asserted, the MF bits are set according to
frequency (DFNH) and division factor low frequency (DFNL) bits in SCCR are set to the value of 0 (÷1
for DFNH and ÷2 for DFNL).
8.2.5
The following pins are dedicated to the PLL operation:
Freescale Semiconductor
Appendix F, “Electrical
•
•
OSCCLK
VDDSYN — Drain voltage. This is the V
should be well-regulated and the pin should be provided with an extremely low impedance path to
the V
close as possible to the chip package.
VSSSYN — Source voltage. This is the V
be provided with an extremely low impedance path to ground. VSSSYN should be bypassed to
VDDSYN by a 0.1 µF capacitor located as close as possible to the chip package.
PLL Pins
DD
Division Factor
power rail. VDDSYN should be bypassed to VSSSYN by a 0.1 µF capacitor located as
DIVF[0:4]
Feedback
Characteristics” and PORESET should be asserted for this time and at least an
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 8-3. System PLL Block Diagram
Comparator
Phase
Delay
Clock
Down
Up
DD
SS
dedicated to the analog PLL circuits. The pin should
dedicated to the analog PLL circuits. The voltage
Charge
Pump
Table
Multiplication Factor
XFC
MF[0:11]
8-1, and the division factor high
VCO
Clocks and Power Control
VCOOUT
VDDSYN
VSSSYN
8-5
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