MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 107

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Figure 3-15. Procedure for Clearing Security on MCF51EM256 Series MCUs via the BDM Port 1
A
A
1
1
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
1. The last three steps are optional, but
1. The last three steps are optional, but
recommended.
recommended.
write csr2[25:24]=11 to initiate BDM reset to halt or
write csr2[25:24]=11 to initiate BDM reset to halt or
hold BKGD=0, apply power, wait N+16 cycles for
hold BKGD=0, apply power, wait N+16 cycles for
secure state unknown,, CPU halted, FEI 10MHz
secure state unknown,, CPU halted, FEI 10MHz
secure state unknown, CPU halted, FEI 10MHz
secure state unknown, CPU halted, FEI 10MHz
write csr2[25:0]=01 to initiate BDM reset to run
write csr2[25:0]=01 to initiate BDM reset to run
write xcsr[31:24]=0x87 to initiate erase/verify
write xcsr[31:24]=0x87 to initiate erase/verify
set PRDIV8 and clock divider fields in CSR3
set PRDIV8 and clock divider fields in CSR3
on-chip flash is erased and un-secure
on-chip flash is erased and un-secure
secure state unknown / unpowered
secure state unknown / unpowered
clock, synchronized to debugger
clock, synchronized to debugger
read xcsr[25] to confirm
read xcsr[25] to confirm
erase/verify complete
erase/verify complete
clock, sync required
clock, sync required
Delay "TBD" cycles
Delay "TBD" cycles
Device is unsecure
Device is unsecure
POR to de-assert
POR to de-assert
of flash memory
of flash memory
Read XCSR
Read XCSR
SYNC
SYNC
xcsr[31:24]==0x87
xcsr[31:24]==0x87
yes
yes
no
no
xcsr[25]=0
xcsr[25]=0
The write IS required
The write IS required
N = number of cycles for SIM to release
N = number of cycles for SIM to release
internal reset. Adder of 16 imposed by the
internal reset. Adder of 16 imposed by the
ColdFire core.
ColdFire core.
BKGD=0 during reset will
BKGD=0 during reset will
ensure that ENBDM comes up "1"
ensure that ENBDM comes up "1"
FLL Enabled, Internal Reference (FEI)
FLL Enabled, Internal Reference (FEI)
at 10MHz is reset default for the ICS
at 10MHz is reset default for the ICS
The FTSR is responsible for supplying
The FTSR is responsible for supplying
an "erase completed and verified" flag
an "erase completed and verified" flag
for use by the core in this step.
for use by the core in this step.
Ways to enter BDM halt mode:
Ways to enter BDM halt mode:
1. BKGD=0 during POR
1. BKGD=0 during POR
2. BKGD=0 during BDM reset
2. BKGD=0 during BDM reset
3. BFHBR=1 during BDM reset
3. BFHBR=1 during BDM reset
4. COP reset and CSR2[COPHR]=1
4. COP reset and CSR2[COPHR]=1
5. Illegal op code reset and
5. Illegal op code reset and
6. Illegal address reset and
6. Illegal address reset and
7. Loss of Lock reset with
7. Loss of Lock reset with
8. Issue BACKGROUND cmd via BDM
8. Issue BACKGROUND cmd via BDM
9. HALT instruction
9. HALT instruction
10.BDM breakpoint
10.BDM breakpoint
11.ColdFire Fault-on-Fault
11.ColdFire Fault-on-Fault
CSR2[IOPHR]=1
CSR2[IOPHR]=1
CSR2[IADHR]=1
CSR2[IADHR]=1
CSR2[LOLHR]=1
CSR2[LOLHR]=1
interface
interface
Of these, only method (1) is
Of these, only method (1) is
guaranteed to work under all
guaranteed to work under all
circumstances.
circumstances.
xcsr[31:24] != 1000 01-1
xcsr[31:24] != 1000 01-1
STOP
STOP
STOP
STOP
error condition
error condition
check code or device
check code or device
already unsecured
already unsecured
.
.
Memory
3-51