MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 616

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Version 1 ColdFire Debug (CF1_DEBUG)
Figure 26-21
command is used as an example:
This process is referred to as cycle stealing. The READ_MEM.B appears as a single-cycle operation to the
processor, even though the pipelined nature of the Operand Execution Pipeline requires multiple CPU
clock cycles for it to actually complete. After that, the debug module tracks the execution of the
READ_MEM.b command as the processor resumes the normal flow of the application program. After
detecting the READ_MEM.B command is done, the BDC issues an ACK pulse to the host controller,
indicating that the addressed byte is ready to be retrieved. After detecting the ACK pulse, the host initiates
the data-read portion of the command.
26-52
1. The 8-bit command code is sent by the host, followed by the address of the memory location to be
2. The target BDC decodes the command and sends it to the CPU.
3. Upon receiving the BDC command request, the CPU schedules a execution slot for the command.
4. The CPU temporarily stalls the instruction stream at the scheduled point, executes the
(TARGET MCU)
read.
READ_MEM.B command and then continues.
BDC CLOCK
TRANSMITS
ACK PULSE
BKGD PIN
16th CYCLE OF THE
LAST COMMAD BIT
TARGET
shows the ACK handshake protocol in a command level timing diagram. A READ_MEM.B
If the ACK pulse was issued by the target, the host assumes the previous
command was executed. If the CPU enters a stop mode prior to executing a
non-intrusive command, the command is discarded and the ACK pulse is
not issued. After entering a stop mode, the BDC command is no longer
pending and the XCSR[CSTAT] value of 001 is kept until the next command
is successfully executed.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
HIGH-IMPEDANCE
32 CYCLES
Figure 26-20. Target Acknowledge Pulse (ACK)
MINIMUM DELAY
FROM THE BDC COMMAND
NOTE
16 CYCLES
SPEED UP PULSE
EARLIEST
START OF
NEXT BIT
HIGH-IMPEDANCE
Freescale Semiconductor