MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 347

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.3.6
In slave mode, the same functions are available after an address match has occurred.
Note that the TX bit in IICC must correctly reflect the desired direction of transfer in master and slave
modes for the transmission to begin. For instance, if the IIC is configured for master transmit but a master
receive is desired, then reading the IICD will not initiate the receive.
Freescale Semiconductor
Reset
RXAK
Field
Field
DATA
IICIF
7:0
1
0
W
R
IIC Data I/O Register (IICD)
IIC Interrupt Flag — The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:
NACK is sent out on the bus by writing 0 or 1 to TXAK after this bit is set.
Response address, and Second Slave address)
0 No interrupt pending.
1 Interrupt pending.
Receive Acknowledge — When the RXAK bit is low, it indicates an acknowledge signal has been received after
the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received.
1 No acknowledge received.
Data — In master transmit mode, when data is written to the IICD, a data transfer is initiated. The most significant
bit is sent first. In master receive mode, reading this register initiates receiving of the next byte of data.
0
7
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IICD register to prevent an inadvertent
initiation of a master receive data transfer.
• One byte transfer including ACK/NACK bit completes if FACK = 0
• One byte transfer including ACK/NACK bit completes if FACK = 1 and this byte is an address byte
• One byte transfer excluding ACK/NCAK bit completes if FACK = 1 and this byte is a data byte. an ACK or
• Match of slave addresses to calling address (Primary Slave address, General Call address, Alert
• Arbitration lost
• Timeouts in SMBus mode except high timeout
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0
6
Table 15-6. IICS Field Descriptions (continued)
Figure 15-6. IIC Data I/O Register (IICD)
Table 15-7. IICD Field Descriptions
0
5
NOTE
0
4
(Received address is stored in data register)
Description
Description
DATA
3
0
0
2
Inter-Integrated Circuit (IIC)
0
1
0
0
15-9