MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 247

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Typically, the interrupt mask level loaded into the processor's status register field (SR[I]) during the
execution of the stop instruction matches the INTC_WCR[MASK] value.
The interrupt controller's wakeup signal is defined as:
10.3.4
The INTC_SFRC register provides a simple memory-mapped mechanism to set a given bit in the
INTC_FRC register to assert a specific level interrupt request. The data value written causes the
appropriate bit in the INTC_FRC register to be set. Attempted reads of this register generate an error
termination.
This register is provided so interrupt service routines can generate a forced interrupt request without the
need to perform a read-modify-write sequence on the INTC_FRC register.
Freescale Semiconductor
MASK
Field
ENB
Offset: CF1_INTC_BASE + 0x1B (INTC_WCR)
6–3
2–0
Offset: CF1_INTC_BASE + 0x1E (INTC_SFRC)
Reset
Reset
7
W
wakeup = INTC_WCR[ENB] & (level of any asserted_int_request > INTC_WCR[MASK])
R
W
R
Enable wakeup signal.
0 Wakeup signal disabled
1 Enables the assertion of the combinational wakeup signal to the clock generation logic.
Reserved, must be cleared.
Interrupt mask level. Defines the interrupt mask level during wait or stop mode and is enforced by the hardware to
be within the range 0–6. If INTC_WCR[ENB] is set, when an interrupt request of a level higher than MASK occurs,
the interrupt controller asserts the wakeup signal to the clock generation logic.
INTC Set Interrupt Force Register (INTC_SFRC)
ENB
1
7
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
0
0
6
0
6
Figure 10-4. Wakeup Control Register (INTC_WCR)
Table 10-6. INTC_WCR Field Descriptions
Figure 10-5. INTC_SFRC Register
0
0
5
0
5
0
0
4
0
4
Description
0
0
3
0
3
SET
0
2
2
0
Interrupt Controller (CF1_INTC)
MASK
0
1
0
1
Access: Read/Write
Access: Write-only
0
0
0
0
10-11