MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 533

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I
LCDWF39
LCDWF40
LCDWF41
LCDWF42
LCDWF43
24.4
This section provides a complete functional description of the <<BLOCK NAME>> block, detailing the
operation of the design from the end-user perspective.
Before enabling the LCD module by asserting the LCDEN bit in the LCDC0 register, configure the LCD
module based on the end application requirements. Out of reset, the LCD module is configured with
default settings, but these settings are not optimal for every application. The LCD module provides several
versatile configuration settings and options to support varied implementation requirements, including:
Freescale Semiconductor
BP[y]LCD[x] Segment-on-Frontplane Operation — If the LCD[x] pin is enabled and configured to operate as a frontplane,
Field
•
Frame frequency
Functional Description
Reset
Reset
Reset
Reset
Reset
the BP[y]LCD[x] bit in the LCDWF registers controls the on/off state for the LCD segment connected between
LCD[x] and BP[y].BP[y] corresponds to an LCD[:0] pin enabled and configured to operate as a backplane that is
active in phase [y]. Asserting BP[y]LCD[x] displays (turns on) the LCD segment connected between LCD[x] and
BP[y].
0 LCD segment off
1 LCD segment on
Segment-on-Backplane Operation — If the LCD[x] pin is enabled and configured to operate as a backplane,
the BP[y] LCD[x] bit in the LCDWF registers controls the phase (A-H) in which the LCD[x] pin is active.Backplane
phase assignment is done using this method.
0 LCD backplane inactive for phase[y]
1 LCD backplane active for phase[y].
W
W
W
W
W
R
R
R
R
R
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
BPHLCD39 BPGLCD39 BPFLCD39 BPELCD39 BPDLCD39 BPCLCD39 BPBLCD39 BPALCD39
BPHLCD40 BPGLCD40 BPFLCD40 BPELCD40 BPDLCD40 BPCLCD40 BPBLCD40 BPALCD40
BPHLCD41 BPGLCD41 BPFLCD41 BPELCD41 BPDLCD41 BPCLCD41 BPBLCD41 BPALCD41
BPHLCD42 BPGLCD42 BPFLCD42 BPELCD42 BPDLCD42 BPCLCD42 BPBLCD42 BPALCD42
BPHLCD43 BPGLCD43 BPFLCD43 BPELCD43 BPDLCD43 BPCLCD43 BPBLCD43 BPALCD43
Figure 24-10. LCD Waveform Registers (LCDWF[:0]) (continued)
7
Table 24-13. LCDWF Field Descriptions
6
5
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Indeterminate after reset
Description
4
3
2
1
LCD Driver Module
24-17
0