MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 119

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

the port returns the logic value of the external pin input for that bit location. When the port bit is configured
as an output (PTxDD[n]=1), a read of the port returns the state of the internal data register bit.
Writing to the data register changes the values of all internal data register bits to the value being written
regardless of the associated DD bit.
4.3.2.2
The PTxDD registers control the direction of the port x pins.
4.3.2.3
Setting a PTxSET bit, sets the corresponding bit of the port data register, PTxD. If a PTxSET bit is cleared
the corresponding bit in the port data register is unchanged. Writes to PTxSET only cause the PTxD to
change. Subsequent writes to PTxD, PTxCLR, or PTxTOG have their own effect in changing the PTxD
register.
Freescale Semiconductor
Reset:
Reset:
PTxDDn
PTxDn
Field
Field
7–0
7–0
W
W
R
R
PTxDD7
PTxD7
Port x Data Register Bits — For Port x pins that are inputs, reads return the logic level on the pin. For Port x
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For Port x pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTxD to all zeroes. Since reset configures all port pins as high-impedence inputs, these zeroes are
not driven onto the pins.
Data Direction for Port x Bits — These read/write bits control the direction of Port x pins and what is read for
PTxD reads.
0 Input (output driver disabled) and PTxD reads return the pin value.
1 Output driver enabled for Port x bit n and PTxD reads return the contents of PTxDn.
0
Port x Data Direction Register (PTxDD)
0
Port x Set Register (PTxSET)
7
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
PTxDD6
PTxD6
0
0
6
6
Figure 4-8. Port x Data Direction Register (PTxDD)
Figure 4-7. Port x Data Register (PTxD)
Table 4-13. PTxDD Field Descriptions
PTxDD5
Table 4-12. PTxD Field Descriptions
PTxD5
0
0
5
5
PTxDD4
PTxD4
0
0
4
4
Description
Description
PTxDD3
PTxD3
3
0
3
0
PTxDD2
PTxD2
0
2
2
0
PTxDD1
PTxD1
0
0
1
1
PTxDD0
PTxD0
0
0
0
0
4-9