MCF51EM128CLL Freescale Semiconductor, MCF51EM128CLL Datasheet - Page 409

• Manufacturer Part Number: MCF51EM128CLL
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLL

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 63
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.5.14 IRTC Configuration Data Register (IRTC_CFG_DATA)
17.5.15 IRTC Daylight Saving Hour Register (IRTC_DST_HOUR)
Freescale Semiconductor
Reset Value
Reset Value
Reset Value
Reset Value
IRTC_CFG_DATA
Field (bcd)
Field (bcd)
IRTC_DST_HOUR
Field
15–1
Field (bin)
Field (bin)
0
Bit Type
Bit Type
Bit Type
Bit Type
Field
Field
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Reserved bits. Read returns zeros.Bit7-Bit1 are reserved for Nucleus family devices, should be written
as 0's.
Flash array select bit — Used as the configuration bit to control the address mapping of the two flash
blocks. Refer to
Figure 17-16. IRTC Daylight Saving Hour Register (IRTC_DST_HOUR)
Bit 15
rsvd
rsvd
Figure 17-15. IRTC Configuration Data Register (IRTC_CFG_DATA)
Bit 7
Bit 15
rsvd
rsvd
—
Bit 7
0
—
—
DST_START_HOUR (tens)
DST_END_HOUR (tens)
Table 17-17. IRTC_CFG_DATA Field Descriptions
Bit 14
rsvd
rsvd
Bit 6
—
0
Section 3.4.2, “Dual Flash
Bit 14
rsvd
rsvd
Bit 6
—
—
Bit 13
rsvd
rsvd
Bit 5
—
0
Bit 13
rsvd
rsvd
Bit 5
—
—
Configuration Data Register
Daylight Saving Hour Register
Bit 12
rsvd
rsvd
Bit 4
—
0
Bit 12
Bit 4
rw
rw
0
0
Controllers,” for details.
Description
Bit 11
rsvd
rsvd
Bit 3
—
Bit 11
0
Bit 3
rw
rw
0
0
DST_START_HOUR
DST_END_HOUR
DST_START_HOUR (units)
DST_END_HOUR (units)
Bit 10
rsvd
rsvd
Bit 2
—
Bit 10
Independent Robust Real Time Clock (IRTC)
0
Bit 2
rw
rw
0
0
rsvd
rsvd
Bit 9
Bit 1
—
Bit 9
Bit 1
0
rw
rw
0
0
CFG0
rsvd
Bit 8
Bit 0
Offset: 0x20
Bit 8
Bit 0
—
rw
Offset: 0x22
0
rw
rw
0
0
0x20
0x21
0x23
0x22
17-25